Overview ASIC Engineer Sr Staff role designed as ‘Hybrid’ with an expectation to work from a Hewlett Packard Enterprise office on average 2 days per week. Who We Are Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture values varied backgrounds and flexibility to manage work and personal needs. We collaborate to drive bold moves and are a force for good. Open up opportunities with HPE. Job Description About HPE Networking At HPE Networking, we are redefining the future of high-performance networking. Our silicon team develops cutting-edge ASICs for next-generation networking platforms. We are looking for a seasoned Design-for-Test (DFT) Engineer to join our team and contribute to the development of advanced 3nm and beyond networking silicon. Job Summary As a DFT Engineer at HPE Networking, you will play a critical role in ensuring the testability and reliability of our high-speed, high-complexity ASICs. You will work closely with front-end design, physical design, and verification teams to architect and implement robust DFT solutions that meet stringent performance and quality requirements. Responsibilities Define and implement DFT architecture for high-performance networking ASICs at 3nm and beyond. Collaborate with RTL and physical design teams to integrate scan, compression, boundary scan, and MBIST features. Develop and validate ATPG patterns for stuck-at, transition, and path-delay fault models. Analyze and resolve DFT-related issues including ATPG DRC violations, simulation mismatches, and timing violations. Apply test constraints and perform STA analysis to ensure timing closure in test modes. Support silicon bring-up and ATE pattern validation using industry-standard formats (STIL, WGL, SVF). Conduct silicon failure analysis and contribute to system-level debug and yield improvement. Automate DFT flows and analysis using scripting languages such as Perl and Tcl. Qualifications 10+ years of hands-on DFT experience in ASIC design, preferably in networking or high-speed digital domains. Deep understanding of fault models: stuck-at, transition, path-delay. Expertise in scan compression, ATPG, and MBIST architecture. Experience with Siemens Tessent tools: SSN, JTAG, IJTAG, MBIST, and memory repair. Proficiency with Synopsys tools: DFT Compiler, DFTMAX, Tetramax, Design Compiler. Simulation experience with Synopsys VCS and Cadence NC-Verilog. Timing analysis using PrimeTime and Cadence Tempus. Able to define test constraints and review STA reports to ensure timing closure in test modes. Debugging with waveform tools such as Novas and SimVision. Familiarity with ATE pattern formats (STIL, WGL) and JTAG SVF. Strong scripting skills in Perl and Tcl for automation and analysis. Preferred Qualifications Experience in silicon bring-up and system-level failure analysis for advanced process nodes (3nm and below). Familiarity with high-speed networking protocols and system-level test strategies. Exposure to yield analysis and production test optimization. What We Can Offer You Health & Wellbeing: Comprehensive benefits for physical, financial, and emotional wellbeing. Personal & Professional Development: Programs to help you reach career goals. Unconditional Inclusion: We value varied backgrounds and offer flexibility to manage work and personal needs. Let's Stay Connected Follow HPE Careers for updates on people, culture, and tech – note: for internal use, external links removed. Job Details Job: Engineering Job Level: TCP_05 Equal Employment Opportunity: HPE is an EEO employer. We do not discriminate based on race, gender, or other protected status; decisions are based on qualifications and business needs. Hewlett Packard Enterprise is an EEO Protected Veteran/ Individual with Disabilities employer. HPE will comply with all applicable laws related to employer use of arrest and conviction records.

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