This job is for a Principal Verification Engineer on the Memory Interconnect Design team. It is a full-time hybrid role with locations in San Jose, CA; Agoura Hills, CA; Morrisville, NC; or Johns Creek, GA. The salary range is described below, and the actual pay will be based on skills and experience. Base pay range $170,000.00/yr - $196,000.00/yr Location: San Jose, CA, Agoura Hills, CA, Morrisville, NC and/or Johns Creek, GA (Hybrid) Type: Full-time Salary Range: $170,000–$196,000 (DOE) No 3rd party agencies or C2C Responsibilities Technical leader for full-chip and block-level verification Define verification plans in coordination with Architects, Logic, and Mixed-Signal Designers Implement testbenches, monitors, and scoreboards using UVM methodology Achieve functional and code coverage goals to ensure quality and completeness Support silicon bring-up, lab testing, and debugging in partnership with the System team Contribute to the development of verification flows, tools, and methodology Mentor and guide junior engineers within the team Requirements Proficient in System Verilog or Verilog with significant UVM methodology experience Significant experience with standard ASIC verification flow/software tools Simulation tools: Synopsys VCS, Cadence Xcelium Coverage & Analysis: Cadence IMC (Incisive Metrics Center) Experience with scripting in Linux/Unix environments Verification of DDR memory interfaces is desirable Experience working in Analog/Mixed-Signal products is desirable Verification Methodologies: SVA (System/Verilog Assertions) is desirable Regression Management: Jenkins (CI/CD Integration) is desirable Demonstrated ability to lead and drive complex technical solutions A strong commitment and ability to work in cross functional and globally dispersed teams MS in Electrical Engineering and 10+ years, or PhD in EE and 7+ years of verification experience Industries Appliances, Electrical, and Electronics Manufacturing Seniority level Mid-Senior level Employment type Contract Related notes Referrals increase your chances of interviewing at OSI Engineering. We’re unlocking community knowledge in a new way with insights added into articles, started with the help of AI.

#J-18808-Ljbffr