Overview Senior PLL Design Engineer (RF and Clocking expertise) – San Diego, CA. Position: Senior IC Design Engineer – San Diego, CA (onsite/hybrid). Employment: Full-Time + Health Benefits + 401K Plan + PTO + Founder Shares. Responsibilities Design and verification of PLLs for RF and clocking applications. Develop high-speed data converters (ADCs, DACs) and RFCMOS front-end design. Collaborate with cross-functional teams to specify, design, and validate IC implementations. Qualifications Experience in PLLs (RF and clocking), high-speed data converters (ADCs, DACs), and RFCMOS front-end design. Strong background in RFIC design, layout, and testing. US Citizenship or US Permanent Residency preferred. Contact Javier Leon - Talent Acquisition, Chelsea Search Group Phone: 619-227-3193 (cell) Email: FJLrecruiter@gmail.com LinkedIn: www.LinkedIn.com/in/JavierLeon

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